Title :
Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes
Author :
Bates, Stephen ; Elliott, Duncan G. ; Swamy, Ramkrishna
Author_Institution :
Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta.
Abstract :
Low-density parity-check convolutional codes (LDPC-CCs) complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice, video, and packet switching networks. In order to use these codes efficiently we must generate termination sequences similar to those used in conventional convolutional codes. In this paper, we present a construction method for termination sequence generation circuits suitable for field-programmable gate arrays and application-specific integrated circuits. This method uses linear algebra to determine the termination sequence for a small number of states of the encoder and converts these solutions into a sequential circuit. Results are presented for several realizations of termination circuits for a (128,3,6) LDPC-CC
Keywords :
convolutional codes; linear algebra; parity check codes; sequential circuits; LDPC-CC codes; application-specific integrated circuits; block-oriented circuits; data communication; error correction codes; field-programmable gate arrays; linear algebra; low-density parity-check convolutional codes; packet switching networks; sequential circuit; termination sequence generation circuits; video streaming; voice streaming; Application specific integrated circuits; Communication standards; Convolutional codes; Decoding; Error correction codes; Field programmable gate arrays; Linear algebra; Packet switching; Parity check codes; Streaming media; Coding and decoding; data communication; error correction codes; linear algebra; packet switching;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2006.880313
