Two-dimensional analysis of emitter resistance in the presence of interfacial oxide breakup in polysilicon emitter bipolar transistors

Two-dimensional computer simulations of the emitter resistance and majority carrier current flow in the presence of interfacial oxide breakup in polysilicon emitter bipolar transistors are shown and compared with published experimental results. The analysis reveals that the behavior of the emitter resistance with oxide layer breakup can be adequately predicted only if 2-D majority carrier current flow is taken into account. The interfacial layer plays an important role in determining the emitter resistivity only in very early stages of oxide layer breakup. Both the experimental data and the analysis reveal a much faster fall-off in emitter resistance with oxide layer breakup than previous 1-D dimensional theoretical analyses have suggested. The 2-D majority carrier modeling presented suggests that the emitter resistance decreases much more rapidly than the current gain in the early stages of oxide layer breakup. Physical mechanisms which explain the differences in the dependence of the emitter resistance and gain on oxide layer breakup are proposed