Title :
A low-power 128-MHz VCO for monolithic PLL ICs
Author :
Kato, Kazuhiko ; Sase, T. ; Sato, Hikaru ; Ikushima, Ichiro ; Kojima, Shin´chi
Author_Institution :
Hitachi Ltd., Ibaraki, Japan
fDate :
4/1/1988 12:00:00 AM
Abstract :
The phase-locked loop (PLL) is implemented by 2-μm bipolar-CMOS (BiCMOS) technology. The power dissipation of the PLL and the voltage-controlled oscillator (VCO) are 100 mW at 64 MHz and 25 mW for 1-128 MHz clock frequencies, respectively. The linearity of the VCO is ±0.5% and the temperature stability is ±50 p.p.m./°C. The center frequency of the VCO is accurately set by using one fixed external resistor. The VCO has an advantage of noise insensitivity. To achieve these features, the VCO design uses an emitter-coupled multivibrator with a built-in timing capacitor and a controlled oscillation loop gain. The PLL can be applied not only to timing recovery for data transmission, but also to frequency synthesis and self-clocking for data recording
Keywords :
monolithic integrated circuits; phase-locked loops; variable-frequency oscillators; 1 to 128 MHz; 100 mW; 2 micron; 25 mW; BiCMOS; ECL; VCO; built-in timing capacitor; center frequency; clock frequency 1 to 128 MHz; controlled oscillation loop gain; emitter-coupled multivibrator; features; fixed external resistor; frequency synthesis; linearity; monolithic PLL; noise insensitivity; phase-locked loop; power dissipation; self-clocking for data recording; temperature stability; timing recovery; voltage-controlled oscillator; BiCMOS integrated circuits; Clocks; Frequency; Linearity; Phase locked loops; Power dissipation; Stability; Temperature; Timing; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
