Digitally programmable analog building blocks for the implementation of artificial neural networks

This paper describes the design, experimental characterization and behavior modeling of a homogeneous set of building blocks necessary to construct in analog hardware feed-forward artificial neural networks. A novel synapse architecture is proposed using a quasi-passive D/A (digital-to-analog) converter followed by a four-quadrant analog-digital multiplier, its main advantages are 1) increased signal input range; 2) improved area/weight resolution ratio; 3) on-chip refreshing of the weight value; and 4) serial loading the weight bits. The neurons are built using MOS (metal-oxide semiconductor) transistors operating in the saturation region and exploiting the inherent quadratic characteristics. Experimental results obtained from a demonstration prototype chip realized in a 1.2 μm double-poly, double-metal CMOS (complimentary MOS) technology show good agreement with the design specifications. A simple application of the proposed building blocks is illustrated based on the mixed-signal simulation of the corresponding behavior models constructed from the experimental characterization data