Title :
Statistical bin limits-an approach to wafer disposition in IC fabrication
Author :
Illyes, Steve ; Baglee, David A G
Author_Institution :
Intel Corp., Rio Rancho, NM, USA
fDate :
2/1/1992 12:00:00 AM
Abstract :
The authors describe the methodology of selecting and implementing statistical bin limits at wafer level test so as to minimize the value added to a defective product, improve the overall outgoing quality and reliability of a product, and provide a tool for helping to drive root cause identification of fabrication problems
Keywords :
CMOS integrated circuits; VLSI; circuit reliability; integrated circuit manufacture; integrated circuit testing; statistical analysis; CMOS processes; IC fabrication; VLSI; defective product; quality improvement; reliability; statistical bin limits; wafer disposition; wafer level test; Automation; Etching; Fabrication; Integrated circuit reliability; Medical services; Merging; Plasma applications; Process control; Production; Strips;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
