• DocumentCode
    761764
  • Title

    Designing a complementary design rule checker based on a binary balanced quad list quad tree

  • Author

    Hsiao, P.-Y. ; Yan, J.-T.

  • Author_Institution
    Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    139
  • Issue
    4
  • fYear
    1992
  • fDate
    7/1/1992 12:00:00 AM
  • Firstpage
    311
  • Lastpage
    322
  • Abstract
    An efficient real time VLSI-CAD tool, the complementary design rule checker (CDRC), composed of one interactive phase and one batch phase is presented. It is a general geometrical design rule model which checks some of the layout constraints in the interactive phase and the other constraints in the batch phase. Those classified constraints are disjointed, and each one of them should be checked only once either during the interactive or batch phase. This system and the embedded layout editor are designed on the basis of the binary balanced quad list quad tree (BBQLQT) and its region query functions. The BBQLQT is more efficient than the most recently published spatial data structure, the Weyten´s quad list quad tree. One day, provided that the BBQLQT has been further improved, the performance of the system will be promoted without giving more additional design effort. This system is therefore proven to be fully modularised and independent of any of the other spatial data structures.
  • Keywords
    VLSI; circuit CAD; circuit layout CAD; BBQLQT; VLSI-CAD tool; complementary design rule checker; design rule checker; design rule model; layout constraints; quad tree; spatial data structures;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings E
  • Publisher
    iet
  • ISSN
    0143-7062
  • Type

    jour

  • Filename
    155987