Abstract :
In data buses used for interconnecting the constituent parts of a computer system, contention can arise if two or more of the modules attempt to acquire control of the bus at the same time. The distributed parallel arbiter is a widely-used means of resolving this contention; it consists of a combinational logic network distributed among all the modules. The time taken for the network to settle is the sum of two components, one representing delays through circuit elements, and the second, propagation delays along bus lines. An earlier calculation of the second of these delays has been found to be incorrect because it took no account of the glitches caused by logic hazards and by the electrical properties of the bus lines- ´wired-OR´ glitches. These errors are corrected, revised expressions for the delay are given, and a method is proposed for improving the performance by bypassing the arbitration process unless contention is actually present.
