Title :
Test synthesis with alternative graphs
Author_Institution :
Dept. of Comput. Eng., Tallinn Tech. Univ., Estonia
Abstract :
Alternative graphs provide an efficient, uniform model describing the structure, functions, and faults in a wide class of digital circuits and for different representation levels. For test pattern generation, they provide a general theoretical basis for combining high-level approaches, symbolic techniques based on binary decision diagrams, and traditional topological algorithms
Keywords :
graphs; logic CAD; logic testing; alternative graphs; binary decision diagrams; high-level approaches; representation levels; symbolic techniques; test pattern generation; topological algorithms; Algorithm design and analysis; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Circuit topology; Costs; Design automation; Digital systems; System testing;
Journal_Title :
Design & Test of Computers, IEEE
