A New Technique for Measuring Gate-Oxide Leakage in Charging Protected MOSFETs

While accurate measurement of gate-oxide leakage in isolated CMOS oxides can be straightforward, it is not the case for CMOS oxides connected to a plasma-charging protection device. In this paper, a method enabling accurate gate-oxide leakage extraction from CMOS transistors directly connected to a gated MOSFET-based charging protection device is described. The method extracts gate-oxide leakage at the bottom side of the gate-oxide from the drain/source terminal of the protected MOSFETs biased into inversion while diverting the parasitic leakages from the protection device into a P⁺ tap sink. The location and design of the P⁺ tap sink play an important role on the success of the method. The method demonstrates a high measurement accuracy over the conventional method with a nearly 99% absorption efficiency of the protection-device-induced leakage by the P ⁺ tap sink, with the test structures used in this study. The method enables a saving of up to 30% of the layout space in the design of the charging test structures in test chips by eliminating usage of the fuse between the protected and protecting devices. A correlation study performed with the data measured by the new method and the conventional method suggests that both protected and protecting transistors can experience gate-oxide damage at the same time during back-end integrated circuit (IC) manufacturing process if the protected transistors violate the gate-charging design rules. It also indicates that the protected transistors have higher chance to receive more severe damage than the protecting transistors due to different oxide damage mechanisms associated with the terminal connectivity of these transistors