Title :
A 14-b 2.5 MSPS pipelined ADC with on-chip EPROM
Author :
Mercer, Douglas A.
Author_Institution :
Analog Devices Inc., Wilmington, MA, USA
fDate :
1/1/1996 12:00:00 AM
Abstract :
A 14-b 2.5 MSPS, multistage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, “write once” EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as ±1.5 LSB and differential nonlinearity errors of ±0.5 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5 V reference and is built on a 2 μm 10 V BiCMOS process and consumes 500 mW of power
Keywords :
BiCMOS integrated circuits; EPROM; analogue-digital conversion; pipeline processing; 10 V; 14 bit; 2 micron; 500 mW; BiCMOS process; MSPS ADC; calibration; differential nonlinearity errors; integral nonlinearity errors; inter-stage gain errors; laser-wafer-trim; multistage pipeline subranging analog-to-digital converter; on chip write once EPROM; package sort; BiCMOS integrated circuits; Calibration; Capacitors; Circuit noise; Dynamic range; EPROM; Packaging; Pipelines; Power supplies; Semiconductor device noise;
Journal_Title :
Solid-State Circuits, IEEE Journal of
