An ECL gate with improved speed and low power in a BiCMOS process

Author

Oklobdzija, Vojin G.

Author_Institution

Integration, Berkeley, CA, USA

Volume

31

Issue

1

fYear

1996

fDate

1/1/1996 12:00:00 AM

Firstpage

77

Lastpage

83

Abstract

An emitter-coupled logic (ECL) gate exhibiting an improved speed-power product over the circuits presented in the past is described. The improvement is due to a combination of a push-pull output stage driven by a controlled current source, thus reducing the static and increasing the dynamic current. This circuit has better driving capabilities and improved speed, yet it uses an order of magnitude less power than a regular ECL gate. Due to its reduced power consumption, this gate allows for a higher level of integration of ECL logic. The realization of this circuit using a regular bipolar process is also possible

Keywords

BiCMOS logic circuits; emitter-coupled logic; logic gates; BiCMOS process; ECL gate; controlled current source; dynamic current; emitter-coupled logic; low power circuit; push-pull output stage; speed-power product; static current; BiCMOS integrated circuits; CMOS technology; Clocks; Coupling circuits; Energy consumption; Frequency; Integrated circuit interconnections; Logic circuits; Logic gates; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.485868

Filename

485868