Title :
Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC
Author :
Lao, Zhihao ; Langmann, Ulrich
Author_Institution :
Mikroelektronik Zentrum, Ruhr-Univ., Bochum, Germany
fDate :
1/1/1996 12:00:00 AM
Abstract :
The design of a low-power Si bipolar 1:16-demultiplexer IC built of 1:4-demultiplexer subcomponents for 10 Gb/s (STM-64) is described. The 1:4-demultiplexers feature an architecture with low component count. Special latches controlled by two clock voltages are used. The 1:16-demultiplexer operates up to 12.5 Gb/s with a power dissipation of only 1.5 W at a single power supply voltage of -3 V
Keywords :
bipolar digital integrated circuits; demultiplexing equipment; integrated circuit design; silicon; 1.5 W; 10 Gbit/s; 1:4-demultiplexer subcomponents; 3 V; STM-64; Si; design; latches; low-power Si bipolar 1:16-demultiplexer IC; Bipolar integrated circuits; Clocks; Communication system control; Energy consumption; Latches; Power dissipation; SONET; Switches; Synchronous digital hierarchy; Voltage control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
