Low Thermal Budget Processing for Sequential 3-D IC Fabrication

Author

Rajendran, Bipin ; Shenoy, Rohit S. ; Witte, Daniel J. ; Chokshi, Nehal S. ; DeLeon, Robert L. ; Tompa, G.S. ; Fabian, R.

Author_Institution

Dept. of Electr. Eng., Stanford Univ., CA

Volume

54

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

707

Lastpage

714

Abstract

Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. The authors demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 degC low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below

Keywords

CMOS integrated circuits; MOSFET; chemical vapour deposition; integrated circuit manufacture; laser beam annealing; 450 C; CMOS transistors; CMOSFET; LPCVD; electrical activation; gate oxide; gate regions; integrated circuit fabrication; laser annealing; low thermal budget processing; low-pressure chemical vapor deposition; source/drain; Annealing; CMOS process; Chemical lasers; Chemical vapor deposition; Heating; Integrated circuit interconnections; MOSFETs; Optical device fabrication; Optical materials; Three-dimensional integrated circuits; CMOSFET; integrated circuit fabrication; laser annealing; low-pressure chemical vapor deposition (LPCVD);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2007.891300

Filename

4142900