Modeling of Inversion Layer Centroid and Polysilicon Depletion Effects on Ultrathin-Gate-Oxide MOSFET Behavior: The Influence of Crystallographic Orientation

An empirical expression is developed for the inversion layer centroid and the polysilicon-gate depletion region thickness for bulk MOSFETs with different crystallographic orientations. In particular, results for the most commonly used wafer orientations, i.e., (100), (110), and (111), are given. These expressions are used to accurately model the inversion charge (Q_inv) and the gate-to-channel capacitance (C_gc) of MOSFETs with gate oxides of nanometric thickness (t_ox < 1 nm) and different surface orientations. The Poisson and Schrodinger equations are self-consistently solved for different values of silicon and polysilicon doping concentrations in these devices. The results show important reductions of both Q_inv and C_gc because of the polysilicon depletion effect and the displacement of the inversion charge centroid from the interface to the silicon bulk as a consequence of quantum effects. These effects are very noticeable for gate-oxide thicknesses of around 1 nm and must be taken into account in the development of accurate MOSFET models. The authors show that this task can be performed by means of a corrected gate-oxide thickness, which includes both the effect of the inversion layer centroid Z_I and the polydepletion region thickness Z _D. To do this, the authors have developed an accurate model for Z_I as a function of the inversion charge concentration, the depletion charge concentration, and the silicon doping concentration for the (100), (110), and (111) wafer orientations. The in-plane channel directions have been swept for each wafer orientation in order to study the validity of the model in depth. Similarly, an expression for Z_D as a function, of the polydoping concentration is provided. The gate-to-channel capacitance is also carefully and extensively analyzed. An analytical model for C_gc is provided and tested for different values of oxide thi- ckness, polysilicon doping, substrate doping, and gate voltage