The Effects of Double-Epilayer Structure on Threshold Voltage of Ultralow Voltage Trench Power MOSFET Devices

The effect of double-epilayer structure on threshold voltage (V _th) has been investigated for p-channel low-voltage (V_ds ) trench power MOSFET devices. By fabricating the device in an intrinsic epilayer grown on the top of a highly doped epilayer, the sensitivity of V_th to the epidoping concentration has been significantly reduced. This reduction is attributed to the fact that in the double-epilayer structure, the compensation effect of epidoping concentration (N_A) is minimized. The V_th variation (sigma_Vth standard deviation) shows a strong dependence on the intrinsic epilayer thickness (t, in micrometers) as: sigma_Vth = 2.4 times 10^5-7.1, while the device-specific on-resistance (sp-R_dson) is linearly proportional to the intrinsic layer thickness. This intrinsic epilayer can thus be utilized to minimize the boron up-diffusion from both the first epilayer and the substrate and further reduces V_th variation. For the p-channel device with a V_ds of 12 V, a 50% lower sigma_Vth has been achieved while maintaining at least the same sp-R_dson with the optimized double-epilayer structure which consists of a 4-mum-thick intrinsic layer and a 2.6-mum-thick first doped epilayer (at 4 times 10¹⁷ cm^-3 or 0.07 Omegamiddotcm). Compared to the single epilayer, the double-epilayer structure also leads to 14% higher device output saturation current and shows the body junction much closer to ideal characteristics (abrupt). This structure enables further reductions of both power consumption and V_th for ultralow voltage power MOSFET