A CORDIC-based unified systolic architecture for sliding window applications of discrete transforms

Author

Kar, Dulal C. ; Rao, V. V Bapeswara

Author_Institution

North Dakota State Univ., Fargo, ND, USA

Volume

44

Issue

2

fYear

1996

fDate

2/1/1996 12:00:00 AM

Firstpage

441

Lastpage

444

Abstract

A CORDIC-based, unified systolic architecture for sliding window applications of the discrete Fourier transform (DFT), the discrete Hartley transform (DHT), the discrete cosine transform (DCT), and the discrete sine transform (DST) is proposed. Compared to earlier works, the proposed scheme offers significant reduction in hardware, particularly for DHT. For an N-point DHT, it requires only [N/2]+1 processing elements, each consisting of one CORDIC processor and two adders

Keywords

Hartley transforms; digital signal processing chips; discrete Fourier transforms; discrete cosine transforms; signal processing; systolic arrays; CORDIC processor; DCT; DFT; DHT; DST; adders; coordinate rotation digital computer; digital signal processing; discrete Fourier transform; discrete Hartley transform; discrete cosine transform; discrete sine transform; sliding window applications; unified systolic architecture; Computer science; Digital signal processing; Discrete Fourier transforms; Discrete cosine transforms; Discrete transforms; Fourier transforms; Hardware; Neodymium; Signal processing algorithms; Virtual manufacturing;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.485943

Filename

485943