DocumentCode
763853
Title
High-speed parallel CRC circuits in VLSI
Author
Pei, Tong-Bi ; Zukowski, Charles
Author_Institution
Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
Volume
40
Issue
4
fYear
1992
fDate
4/1/1992 12:00:00 AM
Firstpage
653
Lastpage
657
Abstract
The use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems is investigated. By generalizing the analysis of a parallel prototype, performance is estimated over a wide range of external constraints and design choices. It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should still enable current CMOS technologies to go well beyond 1 Gb/s data rates
Keywords
VLSI; error detection; parallel architectures; telecommunication equipment; CMOS technologies; VLSI; cyclic redundancy checking; error detection; high speed parallel CRC circuits; parallel architectures; telecommunications systems; Arithmetic; CMOS technology; Circuits; Clocks; Cyclic redundancy check; Data communication; Optical feedback; Polynomials; Prototypes; Very large scale integration;
fLanguage
English
Journal_Title
Communications, IEEE Transactions on
Publisher
ieee
ISSN
0090-6778
Type
jour
DOI
10.1109/26.141415
Filename
141415
Link To Document