DocumentCode :
764115
Title :
Memory technology for post CMOS era
Author :
Brewer, Joe E. ; Zhirnov, Victor V. ; Hutchby, James A.
Author_Institution :
Florida Univ., Gainesville, FL, USA
Volume :
21
Issue :
2
fYear :
2005
Firstpage :
13
Lastpage :
20
Abstract :
One of the tasks of the International Technology Roadmap for Semiconductors (ITRS) Emerging Research Devices (ERD) Technology Working Group (TWG) is to seek out memory technologies presented in the research literature and weigh whether they have the potential to serve in 22-nm and smaller IC generations. The motive for this effort is to develop data that can help guide research investment decisions. In 2004, the ERD TWG summarized some quantitative attributes of four alternative memory approaches, and developed a potential/risk score for each. While this effort falls far short of identifying a specific technology, it is at least a beginning. This article describes the nature of the challenge and reports initial study results.
Keywords :
integrated circuit technology; memory architecture; research and development; risk analysis; technology management; Emerging Research Devices; ITRS; Technology Working Group; memory technology; post CMOS era; potential/risk score; research investment decisions; smaller IC generations; CMOS technology; Central Processing Unit; Circuits; Extrapolation; Information retrieval; Magnetic memory; Microcomputers; Portable computers; Random access memory; Read-write memory;
fLanguage :
English
Journal_Title :
Circuits and Devices Magazine, IEEE
Publisher :
ieee
ISSN :
8755-3996
Type :
jour
DOI :
10.1109/MCD.2005.1414313
Filename :
1414313
Link To Document :
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