A new RISC processor architecture for MPEG-2 decoding

Author

Yamada, Kunihiro ; Kojima, Masanori ; Shimizu, Toru ; Sato, Fumiaki ; Mizuno, Tadanori

Volume

48

Issue

1

fYear

2002

fDate

2/1/2002 12:00:00 AM

Firstpage

143

Lastpage

150

Abstract

Most of the processors for MPEG-2 decoding adopt a four-way or more complex architecture to decrease the calculation cycles, but on the other hand the processors for system control a need more simple architecture. The architecture of an system on a chip (SOC) processor must satisfy both requirements, therefore a two-way RISC processor architecture using a four-multiply-add operation is proposed. Next, a simple IDCT algorithm to decrease the calculation cycles using the four-multiply-add operation is investigated. Also, the data transfer for IDCT is discussed and it is found to be possible to carry out the transfer process in parallel with the calculation. As a result of the evaluation for the total calculation cycle, it is concluded that the two-way RISC processor with a 250 MHz clock can be applied to a SOC for MPEG-2 decoding. In other words, it is suitable for SOCs for DTV and DVD

Keywords

code standards; data compression; decoding; digital signal processing chips; discrete cosine transforms; inverse problems; reduced instruction set computing; telecommunication standards; transform coding; video coding; 250 MHz; DTV; DVD; IDCT algorithm; MPEG-2 decoding; RISC processor architecture; SOC processor; clock; data transfer; four-multiply-add operation; system control; system on a chip; two-way RISC processor architecture; Clocks; Control systems; Decoding; Digital signal processing chips; Embedded computing; Logic; Random access memory; Reduced instruction set computing; Signal processing algorithms; System-on-a-chip;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/TCE.2002.1010104

Filename

1010104