Title :
DLT replacement and synchronization in the digital hybrid PLL frequency synthesizer
Author :
Ryu, Heung-Gyoon ; Ahn, Eung-jin
Author_Institution :
Dept. of Electron. Eng., Chung-Buk Nat. Univ., Cheongju, South Korea
fDate :
2/1/2002 12:00:00 AM
Abstract :
The conventional PLL (phase locked loop) frequency synthesizer has a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are a serious problem because the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit which makes the negligible overshoot and much shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. Also, the hardware complexity and power consumption are decreased to about 28%, as compared with the conventional DH-PLL. The high speed switching characteristic in the frequency synthesis process is verified by computer simulation
Keywords :
digital phase locked loops; direct digital synthesis; synchronisation; table lookup; timing circuits; DH-PLL; DLT-replacement digital logic; digital hybrid PLL; digital look-up table; frequency synthesis; high speed switching characteristic; phase locked loop; timing synchronization circuit; Circuit synthesis; DH-HEMTs; Energy consumption; Frequency synchronization; Frequency synthesizers; Hardware; Phase locked loops; Read only memory; Table lookup; Voltage-controlled oscillators;
Journal_Title :
Consumer Electronics, IEEE Transactions on
DOI :
10.1109/TCE.2002.1010105