FPGA realization of a novel frontend signal processor for pager decoders

This paper proposes a novel frontend signal processor for pager decoders. It consists of noise detector, noise filter, and timing recovery circuit which are designed and implemented into an FPGA chip. Some unique and creative design algorithms for the proposed circuit are developed to improve interference-resistant performance. To testify the reliability and robustness of the proposed circuit, stringent glitches and variation of bit period are purposely added in our FPGA verification and even a much faster system clock of 50 MHz besides the normal one, 76.8 kHz, is utilized to verify our circuit. Actually, these actions often drive our design to take as many ill effects into account as possible and make our circuit more realistic in real operation. The testing results show that our circuit works well under glitches with SNR equal to 8.5 dB and 8% variation of bit period due to Doppler effect, phase changes, and phase jitters