Inhibitory mechanism analysis of complexity O(N) MOS winner-take-all networks

Author

Pedroni, Volnei A.

Author_Institution

Dept. of Electr. Eng., California Inst. of Technol., Pasadena, CA, USA

Volume

42

Issue

3

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

172

Lastpage

175

Abstract

Circuits that perform the winner-take-all (WTA) function are essential building blocks in analog parallel signal processors. We observe that VLSI implementations of the WTA function rely almost invariably on voltage-follower (VF) circuits for the transmission of the inhibitory signal over the network. Basic VF circuits present low resolution, however, and several modifications have been proposed in order to enhance the system performance. These modifications add local feedback to the system, being the global feedback still transmitted by a nested VF circuit. In this paper, we examine the role of MOS/VF circuits in hardware realizations of the WTA function and derive a general method for estimating the resolution gain attained when such modifications are introduced onto a basic VF system. We also examine implementations that do not make use of this kind of inhibitory channel, often presenting lower resolution and/or bigger circuit size

Keywords

MOS analogue integrated circuits; VLSI; analogue processing circuits; circuit feedback; integrated circuit design; operational amplifiers; MOS winner-take-all networks; VLSI implementations; analog parallel signal processors; circuit size; hardware realizations; inhibitory mechanism analysis; local feedback; resolution gain; voltage-follower circuits; Feedback circuits; Hardware; Integrated circuit interconnections; MOS devices; Signal processing; Signal resolution; Silicon; System performance; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.376871

Filename

376871