Author :
Hasuko, K. ; Kano, H. ; Matsumoto, Y. ; Nakamura, Y. ; Sakamoto, H. ; Takemoto, T. ; Fukunaga, C. ; Ishida, Y. ; Komatsu, S. ; Tanaka, K. ; Ikeno, M. ; Nakayoshi, K. ; Sasaki, O. ; Yasu, Y. ; Totsuka, M. ; Hasegawa, Y. ; Mizouchi, K. ; Tsuji, S. ; Ichimiy
Abstract :
A slice test system has been constructed for the ATLAS end-cap muon level-1 trigger. ATLAS is one of the four Large Hadron Collider (LHC) experiment. Although the system has been constructed using prototype application specific integrated circuits (ASICs) and electronics modules, the design scheme of the trigger, readout as well as control logic applied to the system is the final one. The size is about 1/300 of the whole number of channels. The purpose of the slice test is to demonstrate the system design and performance in detail prior to production commitment. In this paper, we discuss the validity of the logic through the comparison of the simulation results, the latency measurement and long run tests.
Keywords :
application specific integrated circuits; data acquisition; high energy physics instrumentation computing; nuclear electronics; readout electronics; trigger circuits; ASIC; ATLAS end-cap muon level 1 trigger system; LHC; Large Hadron Collider; application specific integrated circuits; data acquisition; electronics modules; first integration test; latency measurement; long run tests; readout; simulation results; slice test; Application specific integrated circuits; Circuit testing; Control systems; Large Hadron Collider; Logic circuits; Logic design; Logic testing; Mesons; Prototypes; System testing;
