• DocumentCode
    766484
  • Title

    Planar-DME: a single-layer zero-skew clock tree router

  • Author

    Kahng, Andrew B. ; Tsao, Chung-Wen Albert

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
  • Volume
    15
  • Issue
    1
  • fYear
    1996
  • fDate
    1/1/1996 12:00:00 AM
  • Firstpage
    8
  • Lastpage
    19
  • Abstract
    This paper presents new single-layer, i.e., planar-embeddable, clock tree constructions with exact zero skew under either the linear or the Elmore delay model. Our method, called Planar-DME, consists of two parts. The first algorithm, called Linear-Planar-DME, guarantees an optimal planar zero-skew clock tree (ZST) under the linear delay model. The second algorithm, called Elmore-Planar-DME, uses the Linear-Planar-DME connection topology in constructing a low-cost ZST according to the Elmore delay model. While a planar ZST under the linear delay model is easily converted to a planar ZST under the Elmore model by elongating tree edges in bottom-up order, our key idea is to avoid unneeded wire elongation by iterating the DME construction of ZST and the bottom-up modification of the resulting nonplanar routing. Costs of our planar ZST solutions are comparable to those of the best previous nonplanar ZST solutions, and substantially improve over previous planar clock routing methods
  • Keywords
    clocks; delays; network routing; network topology; trees (mathematics); Elmore delay model; Planar-DME; connection topology; linear delay model; planar-embeddable construction; single-layer zero-skew clock tree router; Binary trees; Circuits; Clocks; Costs; Delay lines; Helium; Routing; Synchronization; Topology; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.486268
  • Filename
    486268