DocumentCode
767461
Title
4.2 Gbit/s single-chip FPGA implementation of AES algorithm
Author
Rodríguez-Henríquez, E. ; Saqib, N.A. ; Díaz-Pérez, A.
Volume
39
Issue
15
fYear
2003
fDate
7/24/2003 12:00:00 AM
Firstpage
1115
Lastpage
1116
Abstract
A high performance encryptor/decryptor core of the advanced encryption standard (AES) is presented. The proposed architecture is implemented on a single-chip FPGA using a fully pipelined approach. The results obtained show that this design offers up to 25.06% less area and yields up to 27.23% higher throughput than the fastest AES FPGA implementations reported to date.
Keywords
circuit optimisation; cryptography; field programmable gate arrays; integrated circuit design; pipeline processing; 4.2 Gbit/s; 4.2 Gbit/s single-chip FPGA implementation; AES cipher algorithm; AES decryption algorithm; Rijndael block cipher algorithm; advanced encryption standard algorithm; area; encryption architecture; fully pipelined approach; high performance encryptor/decryptor core; throughput;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20030746
Filename
1222678
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