Title :
Built-in testable error detection and correction
Author :
Katoozi, Mehdi ; Nordsieck, Arnold W.
Author_Institution :
Boeing High Technol. Center, Seattle, WA, USA
fDate :
1/1/1992 12:00:00 AM
Abstract :
A method for design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented that uses up to 65% less test hardware than customary BIT implementations. A 1-μm CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 μs at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verify the effectiveness of built-in test
Keywords :
CMOS integrated circuits; built-in self test; digital integrated circuits; fault tolerant computing; 1 micron; 10 mus; 16 bit; 25 MHz; BIST; CMOS; EDAC; built-in self test; error detection and correction circuits; fault coverage; speed reduction; Aerospace electronics; Built-in self-test; Circuit faults; Circuit testing; Delay; Design methodology; Error correction; Error correction codes; Hardware; Protection; System testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
