Area-efficient multipliers for digital signal processing applications

An area-efficient parallel sign-magnitude multiplier that receives two N-bit numbers and produces an N-bit product, referred to as a truncated multiplier, is described. The quantization of the product to N bits is achieved by omitting about half the adder cells needed to add the partial products but in order to keep the quantization error to a minimum, probabilistic biases are obtained and are then fed to the inputs of the retained adder cells. The truncated multiplier requires approximately 50% of the area of a standard parallel multiplier. The paper then shows that this design strategy can also be applied for the design of two´s-complement multipliers. The paper concludes with the application of the truncated multiplier for the implementation of a digital filter and it is shown that the signal-to-noise ratio of the digital filter using a truncated multiplier is better than that using a standard multiplier