• DocumentCode
    76780
  • Title

    CMOS-Compatible Self-Aligned In0.53Ga0.47As MOSFETs With Gate Lengths Down to 30 nm

  • Author

    Majumdar, Angshul ; Yanning Sun ; Cheng-Wei Cheng ; Young-Hee Kim ; Rana, Uzma ; Martin, Roberto Martin ; Bruce, Robert L. ; Kuen-Ting Shiu ; Yu Zhu ; Farmer, Damon B. ; Hopstaken, Marinus ; Joseph, Eric A. ; de Souza, Joel P. ; Frank, Martin M. ; Szu-Lin

  • Author_Institution
    Res. Div., T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
  • Volume
    61
  • Issue
    10
  • fYear
    2014
  • fDate
    Oct. 2014
  • Firstpage
    3399
  • Lastpage
    3404
  • Abstract
    We demonstrate self-aligned fully-depleted 20-nm-thick In0.53Ga0.47As-channel MOSFETs using CMOS-compatible device structures and manufacturable process flows. These devices consist of self-aligned source/drain extensions and self-aligned raised source/drain with low sheet resistance of 360 and 115 Ω/sq, respectively. We demonstrate short-channel MOSFETs with gate lengths LG down to 30 nm, low series resistance REXT = 375 Ω·μm, and high peak saturation transconductance GMSAT = 1275 μS/μm at LG = 50 nm and drain bias VDS = 0.5 V. We obtain long-channel capacitive inversion thickness TINV = 2.3 nm and effective mobility μEFF = 650 cm2/Vs at sheet carrier density NS = 5 × 1012 cm-2. Finally, using a calibrated quasi-ballistic FET model, we argue that for LG ≤ 20 nm, μEFF ≈ 1000 cm2/Vs will lead to short-channel MOSFETs operating within 10% of the ballistic limit. Thus, our III-V processes and device structures are well-suited for future generations of high-performance CMOS applications at short gate lengths and tight gate pitches.
  • Keywords
    CMOS integrated circuits; III-V semiconductors; MOSFET circuits; gallium arsenide; indium compounds; CMOS-compatible device structures; CMOS-compatible self-aligned MOSFETs; III-V processes; In0.53Ga0.47As; calibrated quasiballistic FET model; gate lengths; manufacturable process flows; self-aligned fully-depleted channel MOSFETs; self-aligned raised source-drain; self-aligned source-drain extensions; sheet carrier density; size 2.3 nm; size 20 nm; size 30 nm; size 50 nm; voltage 0.5 V; CMOS integrated circuits; Effective mass; Logic gates; MOSFET; Resistance; Transconductance; III-V FETs; MOSFETs;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2014.2335747
  • Filename
    6902852