DocumentCode
768259
Title
Structured test methodologies and test economics for multichip modules
Author
Kornegay, Kevin T. ; Roy, Kaushik
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume
19
Issue
1
fYear
1996
fDate
2/1/1996 12:00:00 AM
Firstpage
195
Lastpage
202
Abstract
Multichip modules (MCMs) use complex digital, analog, and mixed-signal chips on a single substrate from different vendors. To ensure quality of die and the functionality and performance of MCMs, extensive testing is required at all levels. This paper presents structured test methodologies for MCMs. The economics associated with these methodologies and their relative cost at the MCM level are also presented
Keywords
automatic testing; boundary scan testing; delays; design for testability; economics; multichip modules; production testing; MCM level; die quality; multichip modules; relative cost; structured test methodologies; test economics; Assembly; Bonding; Circuit testing; Costs; Design for testability; Monitoring; Multichip modules; Packaging; Probes; Wire;
fLanguage
English
Journal_Title
Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on
Publisher
ieee
ISSN
1070-9894
Type
jour
DOI
10.1109/96.486503
Filename
486503
Link To Document