DocumentCode
768584
Title
Improving Transition Delay Test Using a Hybrid Method
Author
Ahmed, Nisar ; Tehranipoor, Mohammad
Author_Institution
Electr. & Comput. Eng. Dept., Connecticut Univ.
Volume
23
Issue
5
fYear
2006
fDate
5/1/2006 12:00:00 AM
Firstpage
402
Lastpage
412
Abstract
The transition-fault-testing technique combines the launch-off-shift method and an enhanced launch-off-capture method for scan-based designs. The technique improves fault coverage and reduces pattern count and scan-enable design effort. It is practice oriented, suitable for low-cost testers, and implementable with commercial ATPG tools. Scan-based structural tests increasingly serve as a cost- effective alternative to the at-speed functional-pattern approach to transition delay testing. The proposed hybrid technique significantly reduces the design effort and eases the timing closure by selecting a small subset of scan chains to be controlled using LOS. The experimental results also show that the pattern count is reduced and fault coverage is considerably increased. A statistical analysis is required to find the optimum number of LOS-controlled scan chains. Minimizing the number of LOS-controlled scan chains will even further reduces the design effort, and future work must focus on this issue
Keywords
automatic test pattern generation; delays; electronic design automation; logic testing; statistical analysis; commercial ATPG tool; hybrid method; launch-off-capture method; launch-off-shift method; scan-based design; statistical analysis; transition delay fault testing; Clocks; Controllability; Delay; Fault detection; Flip-flops; Lab-on-a-chip; Observability; Signal design; Signal generators; Testing; delay testing; launch-off-capture; test quality;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2006.127
Filename
1704733
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