Title :
A 20-ns 256 K×4 FIFO memory
Author :
Hashimoto, Mime ; Nomura, Masayoshi ; Sasaki, Kenji ; Komatsuzaki, K. ; Fujiwara, H. ; Honzawa, T. ; Abe, Kiyohiko ; Tachibana, Takeshi ; Kitagawa, Norihisa
Author_Institution :
Texas Instrum. Japan Ltd. Design Center, Ibaraki, Japan
fDate :
4/1/1988 12:00:00 AM
Abstract :
A 256 K×4 FIFO (first-in-first-out) CMOS memory with 20-ns access time and 30-ns cycle time is described. To accomplish full static and asynchronous operation, signal synchronizer and arbiter circuits have been developed and implemented into the device. A pair of 120-word×4-bit static memories are furnished to provide 20-ns data access from the very first read cycle. The average current measured at 30-ns read/write operation and the standby current are typically 23 and 1.2 mA, respectively
Keywords :
CMOS integrated circuits; VLSI; integrated memory circuits; 1 Mbit; 1.2 mA; 20 ns; 20-ns; 23 mA; 256 kbyte; 30 ns; 4 bit; ASIC; ASM; CMOS; FIFO memory; VLSI; access time; arbiter circuits; asynchronous operation; custom ICs; cycle time; data access; signal synchronizer; standby current; static memories; static operation; Buffer storage; Circuits; Current measurement; Data communication; Helium; Logic; Memory; Space technology; TV; Video recording;
Journal_Title :
Solid-State Circuits, IEEE Journal of
