Title :
High performance dual-MAC DSP architecture
Author :
Kolagotla, Ravi K. ; Fridman, Jose ; Aldrich, Bradley C. ; Hoffman, Marc M. ; Anderson, William C. ; Allen, Michael S. ; Witt, David B. ; Dunton, Randy R. ; Booth, Lawrence A., Jr.
Author_Institution :
Archit. & Applications Groups, Intel DSP Design Center, Austin, TX, USA
fDate :
7/1/2002 12:00:00 AM
Abstract :
The convergence of voice and video in next-generation wireless applications requires a processor that can efficiently implement a broad range of advanced third generation (3G) wireless algorithms. The micro signal architecture (MSA) core is a dual-MAC modified Harvard architecture that has been designed to have good performance on both voice and video algorithms. In addition, some of the best features and simplicity of microcontrollers has been incorporated into the MSA core. This article presents an overview of the MSA architecture, key engineering issues and their solutions, and details associated with the first implementation of the core. The utility of the MSA architecture for practical 3G wireless applications is illustrated with several application examples and performance benchmarks for typical DSP and image/video kernels. The DSP features of the MSA core include: two 16-bit single-cycle throughput multipliers, two 40-bit split data ALUs, and hardware support for on-the-fly saturation and clipping; two 32-bit pointer ALUs with support for circular and bit-reversed addressing; two separate data ports to a unified 4 GB memory space, a parallel port for instructions, and two loop counters that allow nested zero overhead looping
Keywords :
cellular radio; computer architecture; digital signal processing chips; microcontrollers; speech processing; video signal processing; 32 bit; 3G wireless algorithms; 4 GB; 40 bit; DSP kernels; MSA architecture; bit-reversed addressing; circular addressing; data ports; dual-MAC DSP architecture; dual-MAC modified Harvard architecture; image/video kernels; loop counters; memory space; micro signal architecture; microcontrollers; nested zero overhead looping; next-generation wireless applications; on-the-fly clipping; on-the-fly saturation; parallel port; single-cycle throughput multipliers; split data ALU; third generation wireless algorithms; video algorithm; voice algorithm; voice/video convergence; Algorithm design and analysis; Arithmetic; Convergence; Digital signal processing; Kernel; Microcontrollers; Radio frequency; Random access memory; Signal design; Signal processing algorithms;
Journal_Title :
Signal Processing Magazine, IEEE
DOI :
10.1109/MSP.2002.1012349