Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template

This paper presents a new asynchronous design theory and a novel template for single-track handshaking that targets medium-to high-performance applications. Unlike other single-track templates, the proposed work supports multiple levels of logic per pipeline stage, improving area efficiency by sharing the control logic among more computation logic while at the same time providing higher robustness to timing variability. The proposed template also yields higher throughput than most four-phase templates and lower latency than bundled-data templates. The template was incorporated into the asynchronous ASIC flow Proteus, and experiments on ISCAS benchmarks show significant improvement in achievable throughput per area.