DocumentCode
769942
Title
A 15-gb/s 2:1 multiplexer in 0.18-μm CMOS
Author
Jun-Chau Chien ; Liang-Hung Lu
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Volume
16
Issue
10
fYear
2006
Firstpage
558
Lastpage
560
Abstract
By employing the inductive peaking technique and the super-dynamic flip-flops, a 2:1 multiplexer (MUX) is presented for high-speed operations. The proposed circuit is realized in a 0.18-mum CMOS process. With a power consumption of 110mW from a 2-V supply voltage, the fully integrated MUX can operate at an output rate up to 15Gb/s. From the measured eye-diagrams, the 15-Gb/s half-rate MUX exhibits an output voltage swing of 225mV and a root-mean-square jitter of 2.7ps
Keywords
CMOS integrated circuits; differentiating circuits; flip-flops; multiplexing equipment; 0.18 micron; 110 mW; 15 Gbit/s; 2 V; 225 mV; CMOS process; high speed operations; inductive peaking technique; multiplexers; super dynamic flip flops; Bandwidth; Circuit simulation; Delay; Flip-flops; Intersymbol interference; Latches; Logic circuits; Multiplexing; Tail; Thumb; High-speed latches; inductive peaking; multiplexer (MUX); optical-fiber communications; selectors; super-dynamic flip-flops;
fLanguage
English
Journal_Title
Microwave and Wireless Components Letters, IEEE
Publisher
ieee
ISSN
1531-1309
Type
jour
DOI
10.1109/LMWC.2006.882384
Filename
1704862
Link To Document