A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS

Author

Kromer, C. ; von Buren, G. ; Sialm, G. ; Morf, T. ; Ellinger, F. ; Jackel, H.

Author_Institution

Electron. Lab., Swiss Fed. Inst. of Technol., Zurich

Volume

16

Issue

10

fYear

2006

Firstpage

564

Lastpage

566

Abstract

The implemented static frequency divider provides quadrature (Q) clock outputs and divides frequencies up to 44GHz. The core divider circuit consists of two current-mode logic (CML) latches and consumes 3.2mW from a 1.1-V supply. The divided outputs result in a peak-to-peak and rms jitter of 6.3 and 0.8ps, respectively, and the maximum phase mismatch between the in-phase (I) and Q-outputs amounts to 1ps at an input frequency of 40GHz. The high division frequency is achieved by employing resistive loads, inductive peaking, and optimizing the circuit layout for reduced parasitic capacitances in the latches. The core divider consumes a chip area of 30mumtimes40mum only

Keywords

CMOS logic circuits; circuit optimisation; current-mode logic; flip-flops; frequency dividers; logic design; 1.1 V; 3.2 mW; 40 GHz; 80 nm; CMOS process; circuit layout; circuit optimization; current mode logic latches; inductive peaking; parasitic capacitances; quadrature output; resistive loads; static frequency divider; Clocks; Energy consumption; Frequency conversion; Frequency locked loops; Frequency synthesizers; Latches; Logic circuits; Phase detection; Phase frequency detector; Phase locked loops; CMOS; Clock-and-data recovery (CDR); current-mode logic (CML); frequency divider; phase-locked loop (PLL);

fLanguage

English

Journal_Title

Microwave and Wireless Components Letters, IEEE

Publisher

ieee

ISSN

1531-1309

Type

jour

DOI

10.1109/LMWC.2006.882382

Filename

1704864