The iterative collapse algorithm: a novel approach for the design of long constraint length Viterbi decoders. II

For pt.I see ibid., vol.43, no.2/3/4, p.1409-18 (1995). Part I presented the iterative collapse algorithm (ICA) for obtaining a variety of throughput-complexity tradeoffs for the implementation of parallel VDs and demonstrated that better than linear tradeoff can be obtained in this respect for many combinations of the design parameters M and K. Part I also demonstrated that when (MK+1)/spl les//spl nu//spl les/(M+1)K the ACSUs in the design are fully connected. In this case, clustering of the ACSUs makes no sense since it produces a single cluster containing all the ACSUs. The direct implementation of the decoder requires the full interconnection of L/spl les/2/sup K/ ACSUs (i.e., the ACSU topology is that of a fully connected graph on L nodes denoted K/sub L/). For K/spl ges/3 this is a rather challenging task. The present authors provide efficient means of emulating the ACSU interconnections on a linear or a mesh topology array. Such networks are more suitable for implementation in VLSI. The results presented are quite general and may be easily extended to the emulation of other networks with lower degrees of connectivity than that of the complete graph. The technique presented can be used to build programmable decoders for convolutional and trellis codes in addition to making it possible to build multi-chip VDs on a printed circuit board or as a multi chip module.<>