DocumentCode
770523
Title
High-Linearity Performance of 0.13- 
CMOS Devices Using Field-Plate Technology
Author
Wei, Chien-Cheng ; Chiu, Hsien-Chin ; Feng, Wu-Shiung
Author_Institution
Dept. of Electron. Eng., Chang Gung Univ., Taoyuan
Volume
27
Issue
10
fYear
2006
Firstpage
843
Lastpage
845
Abstract
This letter presents high-linearity 0.13-mum CMOS devices based on field-plate technology. The field-plate technology reduces the electric field between the gate and drain terminals, subsequently forming a field-plate-induced depletion region and reducing the leakage current to significantly improve linearity and power of the CMOS devices. The third-order intermodulation product of 0.13-mum NMOS devices with and without field-plate technology are -41.8 and -32.4 dBm, respectively, for input power of -10 dBm. Experimental results indicate that the field-plate architecture exhibits high linearity and power for CMOS RFIC applications
Keywords
CMOS integrated circuits; MOSFET; leakage currents; 0.13 micron; CMOS RFIC applications; CMOS devices; NMOS devices; depletion region; drain terminals; drain-induced barrier lowering; electric field; field-plate technology; gate terminals; leakage current; CMOS process; CMOS technology; Dielectric devices; HEMTs; Leakage current; Linearity; MODFETs; MOS devices; Radiofrequency integrated circuits; Voltage; 0.13-; Drain-induced barrier lowering (DIBL); field-plate technology; linearity;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2006.882512
Filename
1704918
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