Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment)

Two designs have been presented for high throughput pipelined implementation using field-programmable gate arrays (FPGAs) of the advanced encryption standard (AES). Both are believed to be faster than the existing FPGA designs and achieve throughputs of 30 and 28 Gbps. The fastest design achieves a throughput, for either encipher or decipher, in excess of 30 Gbps using a Xilinx Spartan-III part and allows key changes every 120 cycles. A second design achieves a throughput of 28 Gbps using a Xilinx Virtex-II part and supports both key and encipher/decipher changes every clock cycle. In order to achieve this, careful floor planning and a novel pipelined key expander were developed together with modifications to the MixColumns and composite field implementation of the SubBytes operation. Such an architecture has application for servers supporting multiple AES secure channels and can support, in a multi-channel environment, any feedback mode, including cipher block chaining. Previous pipelined designs have not shown this capability