High-input-sensitivity, low-power 43 Gbit/s decision circuit using InP/InGaAs DHBTs

Author

Ishii, Kazuki ; Nosaka, Hideyuki ; Ida, Minoru ; Kurishima, Kenji ; Shibata, Takuma ; Sano, Eiichi

Author_Institution

Res. Center for Integrated Quantum Electron., Hokkaido Univ., Sapporo

Volume

38

Issue

12

fYear

2002

fDate

6/6/2002 12:00:00 AM

Firstpage

557

Lastpage

558

Abstract

A high-input-sensitivity, low-power decision circuit for 40 Gbit/s-class optical communications systems using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) has been designed and fabricated. These DHBTs exhibit an f_T of 131 GHz and an f_max of 191 GHz at a collector current density of 0.5 mA/μm² and a collector-to-emitter voltage of 1.2 V. The decision circuit was operated at a data rate of up to 43 Gbit/s with a low power consumption of 0.7 W. A high input sensitivity of 50 mV and a wide clock phase margin of 201° at 43 Gbit/s were achieved

Keywords

III-V semiconductors; bipolar digital integrated circuits; decision circuits; gallium arsenide; heterojunction bipolar transistors; high-speed integrated circuits; indium compounds; low-power electronics; optical communication equipment; 0.7 W; 1.2 V; 131 GHz; 191 GHz; 43 Gbit/s; InP-InGaAs; InP/InGaAs double heterojunction bipolar transistor; clock phase margin; input sensitivity; low-power high-speed decision circuit; optical communication IC;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:20020416

Filename

1012852