Clustering analyzer

Author

Cheng, H.D. ; Tong, C.

Author_Institution

Sch. of Comput. Sci., Tech. Univ. of Nova Scotia, Halifax, NS, Canada

Volume

38

Issue

1

fYear

1991

fDate

1/1/1991 12:00:00 AM

Firstpage

124

Lastpage

128

Abstract

A VLSI architecture for implementing the squared-error clustering technique using extensive pipelining and parallel techniques is presented. The proposed architecture performs one pass of the squared-error algorithm, which includes finding the squared distances between every pattern and every cluster center, assigning each pattern to its closest cluster center, and recomputing the cluster centers in O(N+M+K) time units, where M is the dimension of the feature vector, N is the number of sample patterns, and K is the desired number of clusters. It needs O(N×M× K ) time units if a uniprocessor is used

Keywords

VLSI; computerised pattern recognition; computerised picture processing; digital signal processing chips; parallel algorithms; parallel architectures; pipeline processing; DSP; VLSI architecture; image processing; parallel techniques; pattern recognition; pipelining; squared-error algorithm; squared-error clustering technique; Clustering algorithms; Computer science; Data analysis; Data mining; Feature extraction; Image recognition; Pattern analysis; Pattern recognition; Pipeline processing; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.101309

Filename

101309