DocumentCode
771419
Title
Implementation of a Two-Channel LPC Vocoder
Author
Shin, Byoung Cheol ; Lee, Hyeong Ho ; Un, Chong Kwan ; Lee, Sang Zee ; Song, Kil Ho
Author_Institution
Korean Advanced Inst. of Science and Tech.,Taejon, Korea
Volume
31
Issue
7
fYear
1983
fDate
7/1/1983 12:00:00 AM
Firstpage
907
Lastpage
916
Abstract
In this paper we describe hardware implementation of a 2400 bit/s two-channel linear predictive vocoder. The vocoder hardware uses the latest 2900 series "bit slice" microprocessor chips, and 2K RAM\´s and 1K ROM\´s of data memory. The system design is a two bus structure with a 208 ns cycle time. A significant feature of the vocoder is that it is capable of processing two voice channels simultaneously. Throughout the paper, emphasis is placed on details of firmware development of the vocoder system. Efficient design of the vocoder hardware is also discussed.
Keywords
Speech coding; Costs; Hardware; Linear predictive coding; Microprocessor chips; Microprogramming; Narrowband; Random access memory; Signal processing algorithms; Speech analysis; Vocoders;
fLanguage
English
Journal_Title
Communications, IEEE Transactions on
Publisher
ieee
ISSN
0090-6778
Type
jour
DOI
10.1109/TCOM.1983.1095900
Filename
1095900
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