DocumentCode :
771437
Title :
Parallel decoding scheme for a multiple stack algorithm
Author :
Imtawil, V. ; Surakampontorn, W.
Author_Institution :
Dept. of Electr. Eng., King Mongkut´´s Inst. of Technol., Khonkaen, Thailand
Volume :
152
Issue :
6
fYear :
2005
Firstpage :
959
Lastpage :
964
Abstract :
To improve the error performance particularly in a very noisy block that requires excessive tree searches, a parallel decoding scheme for a multiple stack algorithm (MSA) is proposed. In this scheme, apart from the main decoder working on the main stack, a scalable set of multiple decoders working in parallel on their multiple stacks is incorporated. All the decoders are working almost independently with the help of the control processor, where the decoding process and the termination rules are outlined. Two cases, a four-processor MSA and a 16- processor MSA, are employed as examples to investigate the performance of the proposed scheme. Compared with the conventional MSA, extensive computer simulations show that the bit error probabilities are significantly improved.
Keywords :
decoding; error statistics; multiprocessing systems; parallel processing; MSA; bit error probability; error performance; multiple stack algorithm; parallel decoding scheme; processor control; scalability;
fLanguage :
English
Journal_Title :
Communications, IEE Proceedings-
Publisher :
iet
ISSN :
1350-2425
Type :
jour
DOI :
10.1049/ip-com:20050036
Filename :
1561977
Link To Document :
بازگشت