• DocumentCode
    771640
  • Title

    Finite precision implementation of LDPC decoders

  • Author

    Masera, G. ; Quaglio, F. ; Vacca, F.

  • Author_Institution
    Dipt. di Elettronica, Politecnico di Torino, Italy
  • Volume
    152
  • Issue
    6
  • fYear
    2005
  • Firstpage
    1098
  • Lastpage
    1102
  • Abstract
    Low-density parity-check (LDPC) codes are among the most powerful known error correcting codes and they have been shown to achieve performance very close to the Shannon bound. In practical hardware implementations of LDPC decoders, bit error rate performances are affected strongly by fixed-point representation of processed data and, although many papers have been published in recent years on the subject of LDPC codes, only a few of them report results on the effects of finite precision. In the paper two novel arithmetic approximations for the basic processing operations of the decoding algorithm are presented. The two proposed solutions are analysed in terms of bit error rate performance for different finite precision representations of both external and internal data; the estimated performance loss is comparable to that reported by previous works and limited to approximately 0.1 dB for cases of interests. However the proposed solutions support a reduced complexity formulation of the decoding algorithm, so enabling the implementation of flexible decoders that can be adapted to different LDPC codes, block sizes and code rates.
  • Keywords
    approximation theory; block codes; decoding; error correction codes; error statistics; fixed point arithmetic; parity check codes; LDPC; Shannon bound; bit error rate performance; block size; data processing; decoding algorithm; error correcting code; fixed-point representation; low-density parity-check code;
  • fLanguage
    English
  • Journal_Title
    Communications, IEE Proceedings-
  • Publisher
    iet
  • ISSN
    1350-2425
  • Type

    jour

  • DOI
    10.1049/ip-com:20050205
  • Filename
    1561997