Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS

Author

Choi, Chang-Hoon ; Chidambaram, P.R. ; Khamankar, Rajesh ; Machala, Charles F. ; Yu, Zhiping ; Dutton, Robert W.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

49

Issue

7

fYear

2002

fDate

7/1/2002 12:00:00 AM

Firstpage

1227

Lastpage

1231

Abstract

Polysilicon depletion effects show a strong gate length dependence according to experimental p-channel MOS capacitance-voltage (C-V) data. The effect can be influenced not only by gate geometries, but also by dopant profiles in poly-gates. These effects have been modeled and verified using device simulation. Nonuniform dopant distributions in the vertical and lateral direction in the poly-gate cause additional potential drops. The potential drop in the poly-gate becomes critical as the gate geometry is scaled down due to edge and corner depletions resulting from fringing electric fields

Keywords

MOSFET; capacitance; doping profiles; semiconductor device models; CMOS; MOSFETs; Si; corner depletions; device simulation; dopant profile; edge depletions; gate geometric effects; gate length; nonuniform dopant distributions; p-channel MOS capacitance-voltage data; polysilicon gate depletion; potential drop; scaled MOS; Annealing; CMOS process; Capacitance measurement; Doping; Geometry; Instruments; Ion implantation; Lead compounds; MOSFETs; Semiconductor process modeling;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2002.1013280

Filename

1013280