• DocumentCode
    77227
  • Title

    Reverse Electrical Behavior of N-Channel and P-Channel LTPS-TFTs by N2O Plasma Surface Treatment

  • Author

    Ma, W.C.-Y. ; Chi-Yuan Huang ; Tsung-Chieh Chan ; Sheng-Wei Yuan

  • Author_Institution
    Dept. of Electr. Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan
  • Volume
    42
  • Issue
    12
  • fYear
    2014
  • fDate
    Dec. 2014
  • Firstpage
    3825
  • Lastpage
    3829
  • Abstract
    In this paper, the opposite impacts of N2O plasma surface treatment on the n- and p-channel low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are investigated. Significant performance improvement of n-channel LTPS-TFT by N2O plasma surface treatment is observed, including threshold voltage reduction ΔVTH ~ -0.57 V, 1.55× higher transconductance Gm, and 1.82× higher driving current Idrv. However, p-channel LTPS-TFT shows serious performance degradation after N2O plasma surface treatment, including threshold voltage increase ΔVTH ~ -0.99 V, transconductance Gm reduction, and driving current Idrv degradation. The difference of the two mechanisms of N2O plasma surface treatment, namely, plasma induced interfacial layer (PIL) growth effect and trap passivation effect on poly-Si, is elaborated by a process of the PIL removal after the PIL growth. As a result, the trap passivation effect benefits both n- and p-channel LTPS-TFTs. The PIL growth effect shows the opposite impacts on the n- and p-channel LTPS-TFTs, that benefits n-channel LTPS-TFT and degrades p-channel LTPS-TFT seriously. Therefore, the negative impacts of N2O plasma surface treatment on the p-channel LTPS-TFTs can be eliminated by a PIL removal step in the process. These results would be critical for the applications of system-on-panel and 3-D integrated circuit.
  • Keywords
    elemental semiconductors; nitrogen compounds; passivation; plasma materials processing; silicon; thin film transistors; 3D integrated circuit; HfO2 gate dielectric; HfO2; N2O plasma surface treatment; N2O; PIL growth effect; PIL removal step; Si; n-channel LTPS-TFT; p-channel LTPS-TFT; p-channel low-temperature poly-Si thin-film transistors; plasma induced interfacial layer growth effect; system-on-panel; trap passivation effect; Dielectrics; Logic gates; Passivation; Plasmas; Threshold voltage; Transconductance; 3-D integrated circuit (3-D IC); HfO₂; HfO2; interfacial layer; low-temperature poly-Si thin-film transistors (LTPS-TFTs); plasma passivation; plasma passivation.;
  • fLanguage
    English
  • Journal_Title
    Plasma Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0093-3813
  • Type

    jour

  • DOI
    10.1109/TPS.2014.2332187
  • Filename
    6847221