Abstract :
A new parallel multiplier structure is proposed. In this multiplier the operands are partitioned into four groups of bits to produce 16 partial product terms. The novelty of the new structure is that these partial product terms are each repartitioned further into two groups. This will enable the use of parallel counters rather than carry lookahead adders in the intermediate stages. It is shown that the proposed technique has better performance than existing designs with respect to both area and speed.
