Title :
Learning hardware using multiple-valued logic - Part 1: introduction and approach
Author :
Perkowski, Marek ; Foote, David ; Chen, Qihong ; Al-Rabadi, Anas ; Jozwiak, Lech
Author_Institution :
Portland State Univ., OR, USA
Abstract :
The authors propose a learning-hardware approach as a generalization of evolvable hardware. A massively parallel, reconfigurable processor speeds up logic operators performed in learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis in digital-circuit-design automation
Keywords :
genetic algorithms; learning systems; multivalued logic; parallel architectures; cube calculus machine; evolution-based learning; genetic algorithms; learning hardware; logic-synthesis algorithms; massively parallel processor; multiple-valued logic; Biological cells; Computer networks; Evolutionary computation; Field programmable gate arrays; Genetic algorithms; Genetic mutations; Hardware; Humans; Machine learning; Reconfigurable logic;
Journal_Title :
Micro, IEEE
DOI :
10.1109/MM.2002.1013303
