• DocumentCode
    772524
  • Title

    Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits

  • Author

    Thibeault, C. ; Savaria, Y. ; Houle, J.-L.

  • Author_Institution
    Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
  • Volume
    44
  • Issue
    5
  • fYear
    1995
  • fDate
    5/1/1995 12:00:00 AM
  • Firstpage
    724
  • Lastpage
    728
  • Abstract
    In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in Koren and Stapper (1989); one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy
  • Keywords
    equivalence classes; integrated circuit modelling; integrated circuit yield; defect-tolerant IC; defect-tolerant integrated circuits; equivalence proofs; mathematical proofs; model equivalence; yield modeling; Context modeling; Differential equations; Integrated circuit modeling; Integrated circuit yield; Mathematical model; Predictive models; Semiconductor device modeling; Statistical distributions;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.381962
  • Filename
    381962
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=772524