Title :
Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits
Author :
Thibeault, C. ; Savaria, Y. ; Houle, J.-L.
Author_Institution :
Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
fDate :
5/1/1995 12:00:00 AM
Abstract :
In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in Koren and Stapper (1989); one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy
Keywords :
equivalence classes; integrated circuit modelling; integrated circuit yield; defect-tolerant IC; defect-tolerant integrated circuits; equivalence proofs; mathematical proofs; model equivalence; yield modeling; Context modeling; Differential equations; Integrated circuit modeling; Integrated circuit yield; Mathematical model; Predictive models; Semiconductor device modeling; Statistical distributions;
Journal_Title :
Computers, IEEE Transactions on
