An analytical drain current model considering both electron and lattice temperatures simultaneously for deep submicron ultrathin SOI NMOS devices with self-heating

Author

Chen, Yu-Guang ; Ma, Shyh-Yih ; Kuo, James B. ; Yu, Zhiping ; Duton, R.W.

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

42

Issue

5

fYear

1995

fDate

5/1/1995 12:00:00 AM

Firstpage

899

Lastpage

906

Abstract

This paper reports a closed-form analytical drain current model considering both electron and lattice temperatures simultaneously using a quasi-two-dimensional approach for deep submicron ultrathin SOI NMOS devices. As verified by the experimental data, the closed-form analytical model shows a good predication of the negative differential resistance behavior. Based on the analytical model, with a channel length of <0.2 μm, both the effective electron temperature and the lattice temperature are important in determining the negative differential resistance

Keywords

MOSFET; negative resistance devices; semiconductor device models; silicon-on-insulator; analytical drain current model; channel length; deep submicron devices; electron temperature; lattice temperature; negative differential resistance behavior; quasi-two-dimensional approach; self-heating; ultrathin SOI NMOS devices; Analytical models; Electrons; Lattices; MOS devices; Semiconductor thin films; Silicon; Temperature; Thermal conductivity; Thermal resistance; Thin film devices;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.381986

Filename

381986