Title :
A fast algorithm for OR-AND-OR synthesis
Author :
Debnath, Debatosh ; Vranesic, Zvonko G.
Author_Institution :
Dept. of Comput. Sci. & Eng., Oakland Univ., Rochester, MI, USA
Abstract :
Design methods for OR-AND-OR three-level networks are useful for exploiting the flexibility of logic blocks in many complex programmable logic devices. This paper presents T RIMIN, a fast heuristic algorithm for designing OR-AND-OR networks from sum-of-products expressions. Each output of the network realizes a sum-of-complex-terms expression, where a complex term (CT) is similar to a product-of-sums expression. TRIMIN ´s objective is to lower the number of gates in the network. It first generates a set of CTs by applying factorization techniques; then, it solves a set-covering problem by using a greedy algorithm to select a subset of the CTs. The effectiveness of TRIMIN is demonstrated through experimental results.
Keywords :
logic CAD; programmable logic devices; ternary logic; OR-AND-OR three-level network; TRIMIN; complex programmable logic device; complex term; factorization technique; greedy algorithm; heuristic algorithm; logic block; logic design; multilevel synthesis; product-of-sums expression; set-covering problem; sum-of-complex-terms expression; sum-of-products expression; Algorithm design and analysis; Field programmable gate arrays; Greedy algorithms; Heuristic algorithms; Logic design; Logic devices; Logic functions; Network synthesis; Programmable logic arrays; Programmable logic devices;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.816216
